The electronic circuit of an integrated circuit (“IC”) consists of connected components such as transistors, diodes and resistors. The description of the components and their interconnections is called a netlist. Each component is mapped to one or more layout objects that are two-dimensional geometrical objects such as, but not limited to, rectangles, polygons, and paths. Two-dimensional objects also exist for the connections among the components. In turn, these layout objects are used to define regions within a semiconductor die, which will receive different processing steps such as, but are not limited to, dopant implants to produce N-type or P-type regions and thin oxidation regions for transistor gate areas. Typically, layout objects are assigned to specific layers associated with an IC fabrication step such as P-implant or poly deposition. The collection of two-dimensional objects for a given layer is called a layout mask and the collection of layout masks for all layers is called a layout mask data.
Every layout object must satisfy so called design rules that specify geometrical requirements for each object as well as the relationship of an object to other objects. Examples of such requirements include, but are not limited to, such items as minimum width and minimum spacing from one object to another object.
The IC fabrication process is such an extremely complex process so that the sequence of IC fabrication process steps indicated by an IC mask data might not produce the semiconductor structures with sufficient accuracy to assure correct circuit operation. If the circuit performance of a fabricated IC does not meet the required product specifications, then the IC must be discarded. If there are too many discard ICs, then the yield or fraction of good IC will be low and results in higher overall cost for the good ICs.
Any issue with the various steps in IC fabrication procedure could cause the resulting semiconductor structures to deviate sufficiently to cause the fabricated IC to be bad. Examples of important process steps include, but are not limited to lithography, random defect control, and chemical mechanical polishing (“CMP”).
Fabrication process engineers are tasked with ensuring that the resulting fabricated semiconductor structures are accurate as possible as in order to maximize IC yield. Starting at the 130 nm process node and continuing to the current process nodes, the interaction of process and design has made this task much more difficult. This is because it is no longer possible to have a fabrication process recipe that produces the optimal yield for all possible mask layout data. Since it is very difficult to tune fabrication process recipe for each layout mask data, the trend is to adjust mask layout data to ensure the highest yield for a given fabrication process recipe.
IC fabrication process software simulators can model the various steps of an IC fabrication procedure. Traditionally, fabrication process engineers have used these process simulators to guide the development of new fabrication process recipes. Due to the negative effect of the interactions between mask layout and process on IC yield, the use of process simulation has expanded beyond process engineers to mask data preparation and design engineers (“design engineers”). These engineers use process simulations to guide mask layout data creation so that mask data is more compatible with a given process recipe. In effect, mask data is modified in order to increase the eventual fabricated IC yield.
Examples of process simulation software increasingly used by design engineers include, but are not limited to lithography simulation, CMP modeling, and defect sensitivity simulations. The results of these process simulations are used to identify layout configurations with potential yield limiting manufacturing issues and to adjust the mask layout correspondingly.
The next sequence of discussions describe several examples of how process simulations are used to modify the mask layout data. Those versed in the art will recognize that the descriptions are not exhaustive and could be easily extended to other scenarios where mask layout data is adjusted to avoid manufacturing issues using process simulation results.
Lithography
One process simulation increasingly being used by design engineers is lithography simulation. The lithography step is used to transfer mask patterns onto a semiconductor substrate. Any loss of fidelity on the transferred pattern from that of the mask may result in decreased in IC yield. The accuracy of the translation depends on factors including, but not limited to, the optical distortion that depends on layout feature sizes relative to lithography wavelength; the distortion introduced by resist development; the distortion introduced by resist etching process.
In modern day lithography, the shrinking of feature size has by far outpaced the shrinking of wavelength of light sources used in lithography. For current process nodes of 90 nm and below, the distortion introduced by lithography imaging is becoming a dominant factor in accuracy in the translation of design data to wafer images. Various technologies have been developed to solve this problem, including optical proximity correction (“OPC”) and use of phase shift mask (“PSM”). OPC is performed on design data by adding/removing features to layout geometries, in order to compensate the distortion introduced by lithography imaging. PSM is performed by arranging out-of-phase of light waves at the alternative sides of critical dimension (“CD”) features, in order to enhance image printing of these features. The various techniques to improve the printability is collectively called resolution enhancement technique (“RET”) and includes, but is not limited to, OPC, PSM, and line width biasing.
There are two major categories of OPC: rule-based and model-based. Rule-based OPC is performed based on certain preset rules on how OPC features are constructed. It has the advantage of short run time. However, since it does not consider design context of layout geometries, its functionality and effectiveness is very much limited. Model-based or simulation-based OPC is performed based on lithography simulation of layout geometries and features, so it is much more accurate and effective. Prior development of several fast lithography simulators makes model-based OPC practical. One prior art performs OPC iteratively in order to ensure simulation consistent with changes of OPC features; another prior art performs so called aggressive OPC by directly performing inverse transform from desired target printed shapes.
The results and performance of model-based OPC depends on certain “recipes” used including, but not limited to, lithography simulation approach and edge fragmentation methodology. This makes it necessary to verify the results of OPC using so called “OPC verification” tools. OPC verification tools checks how accurately post-OPC layout data print on wafer during lithography process and whether disastrous problems such as, but not limited to, opens and shorts happen to images printed on wafers. OPC verification is performed at one process corner or across a process window. OPC verification tools may find OPC violations that happen due to reasons such as, but not limited to, design patterns beyond usage under which OPC recipes are developed; limitation of OPC recipes on various process corners; and certain design patterns are inherently difficult to be adjusted for OPC. While it is possible to fix OPC violations that are due to limited OPC recipes or incomplete design pattern coverage of OPC recipes through use of specifically design OPC recipes; there are certain OPC violations due to certain design patterns that cannot possibly be fixed by modifying OPC process recipes. OPC violations are normally called “hotspots”; the hotspots that cannot be fixed by adjusting OPC recipes are called “OPC hard hotspots” in design layout. “OPC hard hotspots” can only be fixed by adjusting pre-OPC design layout.
For IC manufacturing process nodes prior to 90 nm process node, the occurrences of OPC hard hotspots are rare. What are identified as “OPC hotspots” with rule-based OPC are likely fixable through use of model-based OPC. Since imaging distortion of layout geometries introduced by lithography does not greatly depend on surrounding geometries; design layout that passes design rule check (“DRC”) are expected to be free of OPC hotspots by using correctly tuned OPC recipes, with very few or none exceptions.
For IC manufacturing process nodes starting from 90 nm process node, the image distortion of layout geometries introduced by lithography depends at a higher degree on its surrounding layout geometries. The implication of this fact is that, in order to generate layouts that have high manufacturing yield, IC fabrication foundries have to provide numerous context-dependent physical design rules that are much more complex than what have been used so far, especial for CD layers. Context-dependent physical design rules not only put a great amount of burden on mask layout designers and layout tools; they are also inherently incomplete. There is virtually no way to capture all possible design patterns with various contexts in a reasonable number of design rules, in the format that may be understood and suitable for use by mask layout designers and layout tools.
Chemical Mechanical Polishing
Another example of process simulation increasingly being used is chemical mechanical polishing (CMP) process simulation to predict such effects as interlayer dielectric (“ILD”) variations. The ILD variations are important since these variations could cause a circuit's interconnection parasitic capacitances to vary significantly from design specifications and results in circuit performances not meeting the design specifications.
The minimum and maximum density design rules are one attempt to mitigate too wide a range of ILD variations. In this approach, dummy geometries called fill are inserted into empty regions in a mask layout in order to get the preferred range of pattern density values. One of the issues with this technique is that a mask layout with a pattern density value within the allowed range may still have ILD variations significant enough to cause circuit performance issues. This is because ILD variations are mostly localized phenomena involving layout geometry and its neighbors while pattern density is computed over a much larger layout region involving much more layout geometries.
CMP process simulators model the ILD variations for a mask layout. These ILD variations can then be fed back to the design phase to make adjustments to mitigate effects on circuit performance. Without the ILD feedback results, the IC circuit designer would be forced to assume overly conservative assumptions that could result in excessive layout area penalty and eventually higher product cost. Even with ILD variation feedback, IC circuit designers would have to accommodate the worst-case ILD variations reported by CMP simulators. A better solution would be to guide the mask layout generation to avoid widely divergent ILD variations.
Particle Defect Density Control
Particle defects are either missing or extra materials caused by particles during fabrication process that could cause such circuit issues as, but not limited to, opens and shorts in a fabricated IC. Defects are random phenomenon that is characterized by a defect density distribution. The lower the defect density distributions for a given fabrication process, the lower the probability of defects causing issues in the fabricated circuits.
Different mask layout data have different sensitivities to particle defects. These sensitivities are a function of such characteristics as, but not limited to, spacing between layout geometries and layout geometry widths. The larger the spacing between geometries, the less susceptible layout geometries are to defects causing electrical shorts. Likewise, the larger a geometry's width, the less susceptible the geometry to the occurrence of opens due to missing material defects.
There are several techniques to gauge the sensitivities of a mask layout to particle defects. One method is to utilize Monte Carlo sampling techniques to inject a sample population of defects into a mask layout and evaluate the occurrence of shorts and opens in the actual mask layout. Another method is to use a critical area analysis (“CAA”) of the mask layout to generate statistics of susceptibility for particles of given size and type. The CAA results are then weighed by the defect density distribution to generate the defect sensitivity for the given mask layout. For any method, a mask layout with a lower defect susceptibility would have a higher probability of higher IC yield.
The standard method of decreasing the susceptibility of a mask layout to defects is increasing the spacing between geometries (“wire spreading”) for extra particle defects and increasing layout geometry widths for missing particle defects. In either scenario, the mask layout must be modified to reduce the sensitivity for the specified defect density distribution.